Summer Internship cum Training Program on VLSI and Embedded Systems Design
(4-6 Weeks)

19th June to 14th July 2017

at The LNMIIT Jaipur

Register Now

About VESD 2017

Summer Internship cum Training Program on VLSI and Embedded Systems Design (VESD 2017) is an annual training cum internship program offered by VLSI and Embedded System Design Research group of the LNMIIT Jaipur . This program started in 2015 and florished in 2016. This year we are organizing VESD with 3 different tracks in a duration of 4 weeks to 6 weeks. Initial 4 weeks includes on campus training on 3 Tracks and participant can utilize the next 2 weeks for project work.

VLSI and Embedded Systems Design Techniques are the main pillar of most of the present research, industrial and commercial activities in Electronics Engineering. This training program focuses on specific design techniques using Xilinx Vivado Design Suite and Zybo Board. It also focuses on embedded system techniques such as RTOS, ARM processors and MIcurium.

The Training program would cover 3 major modules:

  1. Introduction to Digital Circuits and VHDL.
    This would include all combinational and sequential design learning along with VHDL implementation of these systems.

  2. Digital System Design Using FPGAs In this module, Introduction to FPGAs, CPLD, Programmable Logic to ASICs and application design using Zynq FPGA Architecture would be covered.

  3. Embedded Systems This module would cover Introduction to Microtroller and Microprocessor, Embedded System interfacing and programingm ARM architectures, Microblaze and Picoblaze design and development, RTOS and Application development using Inteligi , QT and Qemu

The training program is aimed to become a major outlet and networking opportunity for students, researchers, practitioners and educators interested in VLSI and Embedded System Designs using Xilinx Vivado Design suits and FPGAs.

The training program would use following tools and techniques.

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About the Institute

The LNM Institute of Information Technology ( The LNMIIT ) was founded in 2002 as a joint effort between Rajasthan State and Lakshmi and Usha Mittal Foundation's philanthropic initiative. With the emphasis on quality and rigor in education, the Institute was granted Deemed University status by UGC in 2006 under the De-Novo categor y.

The Institute offers four-year UG (B.Tech.), two-year M.Tech. and Ph.D. programs in the field of Communication and Computer Engineering (CCE), Computer Science and Engineering (CSE), Electronics and Communication Engineering (ECE), Mechanical-Mechatronics Engineering (MME) and Mechanical Engineering (ME). Facilities for PG research leading to Ph.D. are also available in the field of Physics, Mathematics and Humanities and Social Sciences (HSS).

Meet our team


Prof. S.S. Gokhale

Director, The LNMIIT, Jaipur


Prof. Raghuvir Tomar

Professor, ECE, The LNMIIT, Jaipur


Dr. Soumitra Debnath

HoD, ECE, The LNMIIT, Jaipur

Faculty Instructor

Dr. Kusum Lata

Assistant Professor, The LNMIIT, Jaipur

Areas of Expertise: VLSI Design, Formal Verification of Hardware Designs, Digital System designs using FPGAs

Faculty Instructor

Dr. Abhishek Sharma

Assistant Professor, The LNMIIT, Jaipur

Areas of Expertise: Embedded Systems, High Performance Computing and Organic Semiconductors.

Faculty Instructor

Mr. Sandeep Saini

Assistant Professor, The LNMIIT, Jaipur

Areas of Expertise: Digital VLSI circuits, VHDL, Embedded Systems.

Technical Instructor

Mr. Vinod Kumar

Technical Superintendent, The LNMIIT, Jaipur

Areas of Expertise: VHDL, Embedded Systems.

Technical Instructor

Mr. Phoolchand Kumawat

Junior Technical Superintendent, The LNMIIT, Jaipur

Areas of Expertise: VHDL, Embedded Systems.

VESD 2017 Program

VESD 2017 program is as follows.

DateMorning SessionEvening Session
19-06-2017Inauguration and Registration, Introduction to Number System and Boolean AlgebraIntroduction to Vivado Design Suit, First program with VHDL
20-06-2017Combinational Circuits (Adder, Subtractor, MUX, Encoder and Decoder)VHDL codes for Adder, Subtractor, MUX, Encoder and Decoder along with test bench
21-06-2017Sequential Circuits ( Flip flop and latches)VHDL coding for ( Flip flop and latches)
22-06-2017FSM, Moore's and Mealey machineVHDL programs for FMS, traffic light controller
23-06-2017Introduction to CMOS circuit design, NAND, NOR and other basic gatesIntroduction to Microwind and simulation of NAND and NOT gates using Microwind
24-06-2017 Free Weekend. There won't be any official lectures. But doubt clearing session would be organized once in two days.
27-06-2017Complex Static CMOS design techniquesImplementing functions using CMOS design.
28-06-2017Introduction to FPGAsIntroduction to writing Testbenches in VHDL
29-06-2017Complex Programmable Logic Devices (CPLDs)Hands on session using testbenches
30-06-2017Field Programmable Gate Arrays (FPGAs)Hands on with Zynq SoC
01-07-2017Free Weekend. There won't be any official lectures. But doubt clearing session would be organized once in two days.
03-07-2017Alternative FPGA ArchitecturesHands on with Zynq SoC
04-07-2017Basics of Xilinx Seven SeriesHands on with Zynq SoC
05-07-2017Zynq FPGA Architecture.Hands on with Zynq SoC
06-07-2017Embedded System interfacing and programingHands on session using Embedded Artist QSB and Experimental board, using Mded compiler and Lionaro compiler.
07/07/2017ARM architectures: Introduction and programmingHands on with ARM DS-5 and ARM MDK tools
8/7/2017 Free Weekend.
Students can start their project and work parallelly.
10/7/2017Softcore processor and controllersMicroblaze and Picoblaze design and development
11/7/2017Real Time Operating Systems and Linux kernelFree RTOS, MIcurium, linux kernel, Uboot and Device driver programming
12/7/2017Application developmentInteligi, QT and Qemu
13/7/2017Matlab for Embedded SystemsIntel for IoT
14/7/2017Hands on session on application development using Intel Galileo, Centrino and multiple sensorsClosing Ceremony, Certificates distribution.
15/7/2017Free Weekend.
Students can can complete the project work parallelly.
15-07-2017 Onwards For those who want to extend the internship period for next 15 days (Without extra fee and optional)

Important Dates

Registration Deadline : 10th June 2017
Participation Confirmation : 12th June 2017
VESD starts on: 19-06-2017
VESD Concludes on: 14-07-2017

Registration Details

There are limited seats for 30 participants in the workshop which would be filled on first come first serve basis. Registration Fee is as follows:

External Faculty Members : Rs 9,000
External Students : Rs 6,000
LNMIIT Students and Faculty: Rs 4,500
Accomodation (For External participants) Rs 5,000
Accomodation (For internal participants) As per Summer term notice.

LNMIIT mess is available for all the meals on payment basis to all the participants. LNMIIT mess roughly costs around Rs 100 for all three meals of a day.

Payment for Registration and accomodation amount (Single payment for both heads) can be made through NEFT/DD/Local Cheque (We prefer NEFT for faster processing). DD/Cheque should be in favor THE LNM INSTITUTE OF INFORMATION TECHNOLOGY and it should be payable at Jaipur. DD/Local cheque should se sent to Mr. Sandeep Saini (scanned copy/original) on before the registration deadline.

Bank details for NEFT

Bank Name: STATE BANK OF India
Branch of Bank: SECRETARIAT Branch, JAIPUR
Account No: 51089005531
Account type: SAVING
IFSC Code: SBBJ0010031

LNMIIT students can also pay the fee in cash to Mr. Sandeep Saini. Accomodation and mess charges and payments would be as per summer term notice.

After the payments Register online at

Feel free to contact us

Dr. Kusum Lata:
Dr. Abhishek Sharma
Mr. Sandeep

The LNM Institute of Information Technology
Rupa-ki-Nangal, Post-Sumel,Via-Jamdoli
Jaipur-302031, Rajasthan INDIA
Phone: 0141-5191741 (Ext 1208, 1211 and 1204)