Online Training program on Digital Circuit Design and Verification using Vivado

25th May to 12th June 2020

by The LNMIIT Jaipur and CoreEL Technologies Pvt. Ltd.

40 hours hands-on live training/50 hour hands on live training with mini project

Register Now

About the program

The Department of Electronics & Communication Engineering is organizing a Short term training program on “Digital Circuit Design and Verification using Vivado” in collaboration with CoreEL Technologies

Digital Circuit Design and Verification Techniques are the main pillar of most of the present research, industrial and commercial activities in Electronics Engineering. This training program focuses on specific design techniques using Xilinx Vivado Design Suite.

The Training program would cover 3 major modules:

  1. Introduction to Digital Circuits
    This would include all combinational and sequential design concepts.

  2. Digital System Design Using Verilog HDL In this module,the implementation ofDigital Circuits using Verilog HDL will be taught.

  3. System Design and Verification using Vivado This module would cover Introduction FPGA, and how to design and verify the design on FPGA.

Benefits for the participants:

  1. Certificates from CoreEL Technologies and the LNMIIT Jaipur

  2. In depth training on the concepts of Digital Circuits, Verilog HDL and Vivado Design Suite for circuit design and verification

  3. Learn to configure FPGA and verify hardware operation

  4. Learn to configure FPGA architecture features, such as Clock Manager, using the Architecture Wizard

  5. Learn to communicate design timing objectives through the use of Xilinx Design Constraints

  6. Training sessions hand-outs and study material

The training program is aimed to become a major outlet and networking opportunity for students, researchers, practitioners and educators interested in VLSI and Embedded System Designs using Xilinx Vivado Design suits and FPGAs.

About the Institute

The LNM Institute of Information Technology ( The LNMIIT ) was founded in 2002 as a joint effort between Rajasthan State and Lakshmi and Usha Mittal Foundation's philanthropic initiative. With the emphasis on quality and rigor in education, the Institute was granted Deemed University status by UGC in 2006 under the De-Novo categor y.

The Institute offers four-year UG (B.Tech.), two-year M.Tech. and Ph.D. programs in the field of Communication and Computer Engineering (CCE), Computer Science and Engineering (CSE), Electronics and Communication Engineering (ECE), Mechanical-Mechatronics Engineering (MME) and Mechanical Engineering (ME). Facilities for PG research leading to Ph.D. are also available in the field of Physics, Mathematics and Humanities and Social Sciences (HSS).

About CoreEL Technologies and Sandeepani

‘Sandeepani - School of Embedded System Design’ is the training division of CoreEL Technologies (I) Pvt Ltd and a renowned institute for higher learning in Embedded System Design and VLSI technologies. The Professional Development Courses help in honing the basic skills across platforms and methodologies while the Corporate Trainings drive enablement on specific tools and technologies. Sandeepani’s USP lies in being able to deliver comprehensive yet customized courses that improve proficiency on basic concepts as well as advanced tools and methodologies. Since inception in 1992, Sandeepani has trained over 5,000 working professionals and many more students on HDLs, FPGA design, Verification and System Design. Some of the key customers for corporate trainings include Startup companies, Captive MNCs, Design centers, Defense & Aerospace companies.

Meet our team


Prof. Rahul Banerjee

Director, The LNMIIT, Jaipur


Dr. Soumitra Debnath

HoD, ECE, The LNMIIT, Jaipur

Faculty Instructor

Dr. Kusum Lata

Associate Professor, The LNMIIT, Jaipur

Areas of Expertise: VLSI Design, Formal Verification of Hardware Designs, Digital System designs using FPGAs

Faculty Instructor

Mr. Sandeep Saini

Assistant Professor, The LNMIIT, Jaipur

Areas of Expertise: Digital VLSI circuits, VHDL, Embedded Systems.

Industry Expert

Mr. Ankur Sangal

Lead Application Engineer , CoreEL Technologies

Areas of Expertise: VLSI Design, Digital System designs using FPGAs and ASICs

Industry Expert

Mr. Mayank Singh

Application Engineer , CoreEL Technologies

Areas of Expertise: ASIC based Design and Verification using System Verilog with Mentor Graphics Questa Sim and FPGA based Design and Verification using Xilinx Tool set

Course Content

Training program will cover the following contents.

Week 1 (10:00 AM to 12:30 PM)
25-05-2020Introduction to Number System and Boolean Algebra
26-05-2020Introduction to Vivado Design Suit, First program with Verilog
27-05-2020Combinational Circuits (Adder, MUX, Encoder and Decoder)
28-05-2020Sequential Circuits ( Flip flop and latches)
29-05-2020Combinational and Sequential circuit design using Verlog
Week 2 (10:00 AM to 12:30 PM)
01-06-2020Registers and Counters using Verilog
02-06-2020FSM, Moore's and Mealey machine
03-06-2020FSM implementation using Verilog
04-06-2020Introduction to writing Testbenches in Verilog
05-06-2020Introduction to FPGAs
Week 3 (10:00 AM to 12:30 PM)
08-06-20207-Series Architecture Overview
09-06-2020Design and verification using System Verilog
10-06-2020Debug and Clock Management Tile configuration
11-06-2020Introduction to Embedded System Design using Zynq
12-06-2020Adding Peripherals in Programmable Logic

Important Dates

Registration Deadline : 24th May 2020
Participation Confirmation : 24th May 2020
Training starts on: 25th May 2020
Training Concludes on: 12th June 2020

Registration Details

There are limited seats for the participants in the training program and these will be filled on a first come first serve basis.
Registration Fee is as Rs 3000 for all the participants.

Participant can choose one of the option for the registration with the same registration fee.

  1. 40 hours Hands-on Live training

  2. 50 hours Hands-on training with mini project

Payment for Registration amount can be made through NEFT/RTGS (We prefer NEFT for faster processing).

Please mention VLSITraining in the payment remarks while making the payments..

Bank details for NEFT/RTGS only. No cash depostis are allowed


Write the full name as beneficiary name until you reach the charecter limit.
Branch of Bank: C- SCHEME, JAIPUR
Account No: 001201072292
Account type: SAVING
IFSC Code: ICIC0000012

For any queries before or after payment, you can contact Mr. Sandeep Saini at 9983180460 or .

After the payments Register online using this Google form.

List of participants for the program

Sr. No Name Institute
1 Dr. Poonam Kasturi Deen Dayal Upadhyaya College, University of Delhi
2 Ipseeta Nanda K L Deemed to be University
3 Baldev Raj Government College of Engineering and Technology, Jammu
4 Madhavi Gajula Mahatma Gandhi Institute of Technology, Hyderabad
5 Ashish Kumar Singh IIT BHU
6 Sonali Kumari IIT BHU
7 Sisir Kumar Yadav BITS Pilani
8 Aanchal Verma IIT BHU
9 Shalini S Mepco Schlenk Engg College, Sivakasi
10 Kurian C Kurian ER & DCIT
11 Shivam Laddha The LNM Institute of Information Technology, Jaipur
12 Kartik Ahuja The LNM Institute of Information Technology, Jaipur
13 Sangini Gupta The LNM Institute of Information Technology, Jaipur
14 Mehul Dinesh Agarwal The LNM Institute of Information Technology, Jaipur
15 Eashana Bharakatia The LNM Institute of Information Technology, Jaipur
16 Apurv Chaduvula The LNM Institute of Information Technology, Jaipur
17 Manthan Jain The LNM Institute of Information Technology, Jaipur
18 Surbhi Chhabra The LNM Institute of Information Technology, Jaipur

Feel free to contact us

Dr. Kusum Lata:
Mr. Sandeep

The LNM Institute of Information Technology
Rupa-ki-Nangal, Post-Sumel,Via-Jamdoli
Jaipur-302031, Rajasthan INDIA
Phone: 0141-5191741 (Ext 1208, 1211 and 1204)